This invention relates to communication systems and more particularly to systems and methods for receiving modulated signals.
Public wireless radiotelephone systems are commonly employed to provide voice and data communications to subscribers. For example, analog cellular radiotelephone systems, such as designated AMPS, ETACS, NMT-450, and NMT-900, have long been deployed successfully throughout the world. Digital cellular radiotelephone systems such as those conforming to the North American standard IS-54 and the European standard GSM have been in service since the early 1990""s. More recently, a wide variety of wireless digital services broadly labeled as PCS (Personal Communications Services) have been introduced, including advanced digital cellular systems conforming to standards such as IS-136 and IS-95, lower-power systems such as DECT (Digital Enhanced Cordless Telephone) and data communications services such as CDPD (Cellular Digital Packet Data). These and other systems are described in The Mobile Communications Handbook, edited by Gibson and published by CRC Press (1996).
Wireless communications systems such as cellular radiotelephone systems typically include a plurality of communication channels which may be established between a first transceiver (such as a base station) and a second transceiver (such as a mobile terminal). The communication channels typically are subject to performance-degrading environmental effects such as multi-path fading and interference (noise). Fading effects include flat fading which may arise from the interaction of a transmitted signal (the main ray) with reflected versions of the transmitted signal that arrive concurrently at a receiver. Time dispersion, another type of fading, may arise from interaction of the main ray with time-delayed reflections of the main ray. Interference effects may be caused by interaction of non-orthogonal signals generated in the signal medium by sources other than the source of the desired transmitted signal. Equalization techniques such as maximum likelihood sequence estimation (MLSE) may be used to compensate for time dispersion. Interference may be reduced by using antenna beam steering to reduce reception of undesired signals.
Fading is typically a major detriment to the performance of demodulators in communication systems. The receiver of a mobile terminal typically includes a demodulator which may be a coherent demodulator such as a maximum likelihood sequence estimator (MLSE) demodulator (or equalizer). To provide for reliable demodulation of a received signal, an associated channel tracker is typically provided for the demodulator. After acquisition of a communicated signal by the receiver, the channel tracker maintains a channel estimate to provide a coherent reference between the demodulator and the received signal.
Combining demodulation and decoding via feedback from the decoder to the demodulator is a way to improve receiver performance. This may be accomplished by multi-pass demodulation. According to information theory, an optimal receiver jointly performs the operations of demodulation and decoding.
The complexity of such an operation is generally exorbitant especially when interleaving is used in the system. However, it is possible to bridge part of the gap between disjoint and joint demodulation and decoding by the use of feedback from the decoder to the demodulator. This is the idea behind multi-pass demodulation.
An example of such a multi-pass demodulator is described in U.S. Pat. No. 5,673,291 to Dent which is incorporated herein by reference in its entirety. The ""291 patent discusses demodulating a received signal first, then decoding coded symbols, then feeding information obtained by re-encoding the decoder output back to the demodulator to re-demodulate the un-coded symbols with improved performance. The re-encoded symbols are exploited as known symbols with improved performance. The re-encoded symbols are exploited as known symbols by the demodulator, in the same way that it exploits sync symbols, which are true known symbols that have been inserted in the data prior to transmission. The methods and systems of the ""291 patent generally are based in part on knowledge by the receiver of the order of placement of symbols in the transmitted stream and on the placement of any known sync symbols. In another approach, Garr et al. proposed a multi-pass demodulator for fully encoded bit streams with soft feedback to the demodulator. D. Garr et al., xe2x80x9cIterative Decoding of GSM Signals,xe2x80x9d Conference on Information Sciences and Systems, Princeton University, March 1988. Yet another proposed approach as described in, for example, Berrou et al., xe2x80x9cNear Shannon Limit Error-correcting Coding and Decoding: Turbo-codes (1),xe2x80x9d Proceedings of the IEEE International Communication Conference, pages 1064-1070, 1993, proposes the use of turbo codes in which parallel concatenation of two recursive convolutional codes are used. Likewise, serial concatenation of two recursive convolutional codes was proposed in Benedetto et al., xe2x80x9cSerial Concatenation of Interleaved Codes: performance Analysis, Design and Iterative Decoding,xe2x80x9d TDA Progress Report 42-126, Politechnico Di Torino, Italy, Aug. 15, 1996.
A problem is encountered with methods such as that proposed in the ""291 patent and for communications systems having unencoded bit classes. Examples of such codes associated with various telecommunication standards currently proposed are shown in FIGS. 1A and 1B. FIG. 1A illustrates a voice coding system such as that described for the IS-136 specification. FIG. 1B shows a similar format for the IS-641 specification. As shown in FIG. 1A coding system 10 includes a Vector-Sum Excited Linear Prediction (VSELP) vocoder outputting 159 bits as a data frame. The bits are designated into 3 coding classes referred to as Class 1A, Class 1B and Class 2. Twelve bits designated as Class 1A are first passed to CRC error detection coder 14 which appends a Cyclical Redundancy Check (CRC) error detection code to the twelve Class 1A bits before passing them to convolutional encoder 16. An additional 65 bits, classified as Class 1B, are passed directly to convolutional encoder 16 without error detection coding. Finally, 82 bits, classified as Class 2 bits, are passed directly to interleaver 18 without error detection or correction encoding. The output of convolutional encoder 16 and the unprotected Class 2 bits are passed to 2-slot interleaver 18.
Interleaver 18 breaks up the original data frame into two frames, each containing half the original information and each of which is placed in one of two adjacent slots (i.e. sequential transmission windows) by slot formatter 19 for transmission by a modulator (not shown).
Referring now to FIG. 1B, the structure of coding under the IS-641 standard will now be described. Adaptive Code Excited Linear Prediction (ACELP) vocoder 22 of coding system 20 provides a data frame of 148 bits. 48 of the bits are classified as Class 1A and pass to CRC error detection coder 24 where an error detection code is appended to the bits. An additional 48 of the bits from the 148 bit data frame are treated as Class 1B bits and provided to convolutional coder 26 without error detection coding. The remaining 52 bits are treated as Class 2 bits and provided directly to interleaver 28 without coding. The Class 1A and 1B bits are passed through convolutional encoder 26 and, in turn, the code is punctured by circuit 27 to provide a total of 260 bits to two-slot interleaver 28 when combined with the 52 Class 2 bits. As described above with respect to FIG. 1A, interleaver 28 and slot formatter 29 implement interleaving by dividing the 148 bits from source 22 into two separate slots which are provided to a modulator for transmission.
While these various approaches provide the potential for improved signal reception, there continues to be a need for improvements in performance of receivers for modulated signals containing encoded and unencoded data. There is further a need for such improvements which may be utilized with existing communication protocol standards.
It is, therefore, an object of the present invention to resolve the problem of reception errors in wireless communication systems by providing methods and systems for receiving a modulated signal including encoded bits and unencoded bits using multi-pass demodulation.
It is an additional object of the present invention to provide such systems and methods which may be utilized with existing communication protocol standards.
It is a farther object of the present invention to provide such systems and methods which may be beneficially utilized with MLSE type demodulators providing both hard and soft output information.
It is a further object of the present invention to combine the reduced complexity of the M-algorithm in the demodulator with the feedback information of multi-pass demodulation to obtain an efficient high performance receiver.
These and other objects are provided according to the present invention, by providing methods and systems for receiving a modulated signal including symbols representing both encoded and unencoded bits from a data (e.g., speech) frame where a received slot is first demodulated and the encoded bits are decoded. The decoded bits are then utilized to constrain demodulation during a second demodulation of a received slot. The encoded bit positions from the constrained second demodulation are, in turn, encoded to generate bit estimates for the received slot. This information is combined with the output of the constrained second demodulation for unencoded bits to provide a received data frame estimate which has been shown to provide improved reliability for both encoded and unencoded bits.
In particular, a method for receiving a modulated signal including a plurality of sequentially transmitted slots containing symbols representing encoded bits corresponding to a first subset of bits from a data frame and unencoded bits corresponding to a second subset of bits from the data frame is provided. A first slot is received and demodulated to provide a first slot estimate having encoded bit positions and unencoded bit positions. The encoded bit positions of the first slot estimate are decoded to provide first decoded bit estimates. The first slot is then constrained demodulated, preferably convolutionally, to provide a second slot estimate having encoded bit positions and unencoded bit positions with the second slot estimate of encoded bit positions constrained according to the first decoded bit estimates. The encoded bit positions of the second slot estimate are decoded to provide second decoded bit estimates which are combined with the unencoded bit positions of the second slot estimate to provide a received data frame estimate.
In a further embodiment of the methods of the present invention, after decoding to obtain a first slot estimate, any errors are detected in the first decoded bit estimates and the encoded bit positions of the second slot estimate are not used to generate the second decoded bit estimates if an error is detected. Error detection may be provided by including at least one error detection bit, such as CRC bits, in the first decoded bit estimates and detecting an error in the first decoded bit estimates based on the at least one error detection bit.
Constrained demodulation operations according to an embodiment of the present invention may include discarding during demodulation any candidate bit path having a bit estimate in a location corresponding to one of the encoded bit positions of the first slot which differs from an associated one of the first decoded bit estimates. Alternatively, a metric of any candidate bit path having a bit estimate in a location corresponding to one of the encoded bit positions of the first slot which differs from an associated one of the first decoded bit estimates may be biased to disfavor that candidate bit path. Furthermore, the decoder may output an associated soft reliability value for each first decoded bit estimate and the first slot may then be constrained convolutionally demodulated by biasing a metric of any candidate bit path having a bit estimate in a location corresponding to one of the encoded bit positions of the first slot which differs from an associated one of the first decoded bit estimates based on the associated soft reliability value of the associated one of the first decoded bit estimates.
In another embodiment of the present invention, multi-pass demodulation is provided recursively by repeating the constrained demodulating and the decoding the encoded bit positions of the second slot estimate operations using the decoded bit estimates from a most recent decoding step to constrain the constrained demodulating until a recursion counter reaches a limit and combining a final set of decoded bit estimates and the unencoded bit estimates of a final slot estimate to provide the received frame estimate. Alternatively, recursive operations may continue until a reliability criteria is satisfied. The reliability criteria may be a performance.
In a further aspect, the first demodulation operation may be performed using a differential decoder. Alternatively, a differential decoder may be utilized if a reliability criteria is satisfied and a convolutional decoder may be used otherwise. The present invention may also be utilized with per-survivor processing in the constrained demodulating operations. Furthermore, separate buffer memory may be utilized for each pass of demodulation or a single buffer may be used an overwritten in each pass.
The benefits of the present invention in another embodiment may be realized where the transmitted slots contain interleaved data transmission. The first slot may be received before the second slot. The first decoded bit estimates, bits from the unencoded bit positions of the first slot estimate and unknown bits corresponding to the second segment of bits may be combined to provide a regenerated slot and the constrained demodulating operations may be constrained by using the regenerated slot to restrict trellis transitions during demodulation. Alternatively, trellis transitions may be constrained during demodulation by biasing a metric of selected candidate bit paths based on the regenerated slot.
In another embodiment of the present invention the first slot is constrained trellis demodulated using an M-algorithm having a plurality of trellis stages. The number of surviving states for at least one of the plurality of trellis stages may be specified. The number of surviving states for the plurality of trellis stages further may be specified so as to allow only acceptable paths to continue as surviving states.
In a further aspect of the present invention, a method is provided for receiving a modulated signal including a plurality of sequentially transmitted slots. A first slot is received and demodulated to provide a first slot estimate. The first slot estimate is decoded to provide first decoded bit estimates. The first slot is then constrained demodulated to provide a second slot estimate in which a plurality of bit positions in the second slot estimate are constrained to equal associated ones of the first decoded bit estimates. The second slot estimate is decoded to provide a received data frame estimate. The constrained demodulating operations and the decoding the second slot estimate operations are recursively repeated using the data frame estimate to constrain the constrained demodulation step.
In a system aspect of the present invention, a receiver is provided for receiving a modulated signal including a plurality of sequentially transmitted slots containing symbols representing encoded bits corresponding to a first subset of bits from a data frame and unencoded bits corresponding to a second subset of bits from the data frame. The receiver includes a receiver circuit configured to receive the transmitted slots and a first demodulator coupled to the receiver circuit and configured to generate a first slot estimate from a received slot. A first decoder is coupled to the demodulator so at to provide first decoded bit estimates from the first slot estimate and a constraint slot. A constrained demodulator configured to generate a second slot estimate based on the constraint slot is also provided. A second decoder is provided which is coupled to the constrained demodulator so as to provide second decoded bit estimates from the second slot estimate. Means are also included for combining the second decoded bit estimates and unencoded bit positions of the second slot estimate to provide a received data frame estimate.
While the present invention has been described above primarily with reference to method aspects, it is to be understood that the present invention also encompasses systems aspects including systems configured to carry out the methods of the present invention. Accordingly, the present invention provides novel approaches to multi-pass demodulation which provide improved receiver performance.